Challenges towards Exascale Computing

Overcoming the Barriers to Exascale through Innovation

Stephen S. Pawlowski (Intel)

Abstract:

Exascale computing at reasonable power levels requires a tectonic shift in our computing paradigms: we must run at lower frequencies than the extrapolation of current designs would seem to allow. This in turn poses enormous challenges for exascale software and applications: if a processor core runs at a billion operations per second, and we need to do billion, billion(1018) operations per second, we will need to identify and use billion way parallelism to sustain exascale computing. This amount to at least a 10,000-fold increase in parallelism from that utilized in today's most parallel applications. In addition, to get to exascale, challenges exist on the reliability and memory front. In his talk, Steve will discuss the unique challenges posed by exascale as well as the laboratory partnerships that Intel is developing in Europe and the US aimed at providing not only new scientific, engineering, and societal exascale applications, but also providing feedback into the architectures needed for exascale.

Bio:

Stephen S. Pawlowski is an Intel Senior Fellow, chief technology officer for the Intel Architecture Group, and general manager for Cross-IAG Architecture and Pathfinding for Intel Corporation. He is responsible for ensuring architectural consistency across all Intel® Architecture and implementation of initiatives such as security and manageability across Intel® Core? and Atom? product lines.
Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products and was the co-architect for Intel's first P6 based server chipsets. He helped define the system bus interfaces for Intel's P6 family processors, the Pentium® 4 processor and Itanium? processor. He also created and led the research for Intel's agile radio architecture for a future generation of wireless products, he was the director of Corporate Technology Group's Microprocessor Technology Lab and prior to his current assignment, he was the CTO of the Digital Enterprise Group (DEG) and General Manager of the DEG Architecture and Planning.
Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's degrees in electrical engineering technology and computer systems engineering technology, and received a master's degree in computer science and engineering from the Oregon Graduate Institute in 1993.
Pawlowski holds 56 patents in the area of system, and microprocessor technologies. He has received three Intel Achievement Awards.