Challenges towards Exascale Computing

Performance, Productivity and Programmability: The Coming of Age of FPGA Code Accelerators

Walid A. Najjar (University of California, Riverside)

Abstract:

A large number of studies have repeatedly demonstrated the ability of FPGA accelerators to achieve one to four orders of magnitude speed-ups over software execution. This is due to (1) the elimination of the overhead endemic in the stored program model (load, store and control instructions), (2) the deployment of large scale operation, loop and thread parallelism, and (3) customized pipelined data-paths supporting data reuse and variable bit width data. However, their poor programmability continue to be the main obstacle to their wider adoption. ROCCC (Riverside Optimizing Compiler for Configurable Computing) is an innovative C to VHDL compilation framework specifically focused on FPGA-based code acceleration. Its focus is on extensive and unique loop analysis techniques to implement advanced compile time transformations and optimizations aimed at generating an efficient circuit from a loop nest. ROCCC 2.0 goes a step further in bridging the gap between the temporal programming model inherent in C and the spatial programming model specific to hardware by supporting a bottom-up modular design approach and the reuse of existing codes while maintaining full compatibility with C. Existing C, VHDL and netlist modules can be imported into C source codes. ROCCC 2.0 is a free and open source tool that has been ported to a variety of platforms including the Convey Computers HC-1 and FPGA boards from Pico Computing. Applications developed with ROCCC, including image processing, computer vision, bioinformatics and data mining, have been shown to achieve two to four orders of magnitude speed-up over CPUs.

Bio:

Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His research interests are in the fields of computer architecture and compiler optimizations, embedded systems and sensor networks. Lately, he has been very active in the area of compilation for FPGA-based code acceleration and reconfigurable computing. NSF, DARPA and various industry sponsors have supported his research.
Walid received a B.E. in Electrical Engineering from the American University of Beirut in 1979 and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. From 1989 to 2000 he was on the faculty of the Department of Computer Science at Colorado State University, before that with the USC-Information Sciences Institute. He currently serves as Associate Editor for IEEE Transactions on Computers and IEEE Computer Architecture Letters and has served on the program committees for a number of leading conferences. He was a recipient of the IBM Faculty Award and was elected Fellow of the IEEE and the AAAS.